Solid state analog computer-type calibrator for a radio interferometer

ABSTRACT

A solid state multiplier for an analogue computer which permits the unique determination of the bearing and elevation angles of arrival of a signal ray. The multiplier provides solutions to a set of interferometer descriptive equations corresponding to data supplied by three two-element interferometers and a centralcrossed Adcock array.

United States Patent Inventor Appl. No.

Filed Patented Assignee William Christian McClurg. Wethersfield, Conn.771,042

Oct. 28, 1968 Jan. 12, 1971 The United States of America as representedby the Secretary of the Army by mesne assignments to SOLID STATE ANALOGCOMPUTER-TYPE CALIBRATOR FOR A RADIO INTERFEROMETER 6 Claims, 6 DrawingFigs.

[1.8. CI 235/189, 235/194, 235/186 Int. Cl G06g 7/22, 006g 7/16 Field ofSearch 235/186,

Trl'gggr Compare ircuit [56] References Cited UNITED STATES PATENTS3,187,169 6/1965 Tramme1l,1r.etal 235/189 3,384,738 5/1968 Warrick, Jr235/189 3,430,855 3/1969 Hartwell et a1. 235/189X 3,459,932 8/1969 Hueyet a1 235/197 Primary Examiner-Malcolm A. Morrison AssistantExaminer-1oseph Fv Ruggiero Att0rneysHarry M. Saragovitz, Edward J.Kelly, Herbert Berl and Milton W. Lee

ABSTRACT: A solid state multiplier for an analogue computer whichpermits the unique determination of the bearing and elevation angles ofarrival of a signal ray. The multiplier provides solutions to a set ofinterferometer descriptive equations corresponding to data supplied bythree two-element interferometers and a central-crossed Adcock array.

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SOLID STATE ANALOG COMPUTER-TYPE CALIBRATOR FOR A RADIO INTERFEROMETERBACKGROUND OF THE INVENTION This invention pertains to multipliers asused in an analogue computer network and, more particularly, to anelectronic multiplier for providing solutions to a corresponding set ofin terferometer descriptive equations.

The use of trigonometric multipliers and electronic resolvers, in theprior art, has in general presented numerous problems. In the case ofelectromechanical devices such as servomechanisms for driving mechanicalor electrical cams and potentiometers, limitations arise due to therequirement for large, bulky, and heavy regulated high voltage powersupplies. In mechanical systems, poor resolution, low reliability, andwear of moving parts become very evident limitations. Prior art deviceshave also included induction resolvers which utilize a driving servo,but, in this case also, limitations exist in the form of limitedresponse of the driving servomotor.

SUMMARY OF INVENTION It is the general purpose of this invention toprovide a solid state multiplier which embraces all the advantages ofthe prior art electromechanical multipliers and resolvers but isconsiderably smaller in size, all electronic, more reliable, lighter inweight, and requires much less power to operate than itselectromechanical counterparts. To attain this, the instant inventioncontemplates a unique circuit arrangement for integrating a gatingsignal to produce a linear ramp voltage. A reference input signal iscompared to the ramp signal and upon coincidence of the two signals asample and hold circuit is triggered for sampling and holding theinstantaneous value of the input signal. A subsequent modulation of thesampled signal produces an output analagous to the output of theequivalent electromechanical device.

BRIEF DESCRIPTION OF THE DRAWINGS The exact nature of this inventionwill be readily apparent from consideration of the followingspecification relating to the annexed drawings in which:

FIG. I shows a typical prior art electromechanical resolver as used in amechanical analogue computer;

FIG. 2 shows the equivalent of FIG. 1 as visualized by the instantinvention;

FIG. 3s a waveform diagram illustrating typical waveforms at variouspoints in the circuit during normal operation;

FIG. 4 shows circuitry for the gate generator of FIG. 2;

FIG. 5 shows circuitry for the ramp generator of FIG. 2; and

FIG. 6 shows circuitry for the compare and sample-hold arrangement ofFIG. 2.

DESCRIPTION OF THE INVENTION The present invention is an electronicanalogue of a wideband high frequency radio direction finder system ofthe interferometer type. The system permits measurement of both theazimuthal and elevation angles of arrival of a signal ray and is a truedirection finder.

The electrical output from a given two-element radio interferometerconsisting of isotropic elements may be converted to an angle 1 which isa function of wavelength, angle of incidence, and angle of azimuth ofthe arriving ray. The value of I is not necessarily unique; ambiguitiesmay be present and these need to be resolved to obtain a unique answer.

The D (n, a) function is ofa form that can be closely approximated by aproduct of functions in the analogue computer of FIG. 2. The philosophythat is adopted here is a system approach using electronic componentsthat are combined in a novel way. Specifically, one knows the law of theinterferometer. Hence the analogue computer of FIG. 2 can be programmedto generate the same kind of output voltage function as the radiointerferometer. Two sets of outputs, one from the interferometer andanother from the computer can be displayed on the same cathode-rayoscillograph for alignment purposes. The input control dials of thecomputer, shown as n, 6 and a in FIG. 2, can be manually adjusted sothat the two displays are made to coincide. No other combination of 0and a values can produce this set of coincidences.

FIG. 2 shows a functional block diagram of an assembly of analoguecomputer type components which will permit the generation of the P (n, 060 functions by appropriate hand settings of the three dials labeled n,0 and a respectively. A well regulated reference voltage proportional ton rrwhich represents the number of radians that theinterferometer basecovers, is supplied to a linear potentiometer I0. Unity-gain operationalamplifiers are used to interconnect in cascade the linear potentiometerl0, sine potentiometer ll, cosine potentiometer 12, and the solid statemultiplier. The input to the multiplier is proportional to, n 11' sin V4cos a, i.e. angle 1 As seen in FIG. 2, a balanced supply voltage isapplied through operational amplifiers to a pair of diametrically 0pposed taps on potentiometer 11. The other pair of taps of thepotentiometer is grounded. Each quadrant of the resistive element istapered to give a sinusoidal output when a specified load is connectedbetween the slider and ground. The output of potentiometer 11 takes theform on n 1r sin 0 and is fed to potentiometer 12 for producing aproduct n 1r sin 6 cos a. This signal is applied to a comparator 23,shown in detail in FIG. 6, where it is amplitude compared to a rampsignal eminating from ramp generator 21. Comparator 23 functions in sucha rapid manner that the input :1 1: sin 0 cos 01 appears to be aconstant DC voltage at any particular time.

The ramp signal of FIG. 3 (0), produced by ramp generator 21 and shownin detail in FIG. 5, represents the number of radians over which theinterferometer base extends and covers 10 1r radians in the illustrationshown in FIG. 3.

As shown in FIG. 2, a 60 cycle line voltage at 0 phase angle is appliedsimultaneously to a gate generator 20 (shown in FIG. 4) and asample-hold circuit 22 (shown in FIG. 6). The gate generator 20functions in the dual capacity of gating the ramp generator 21 for theentire desired period of the ramp signal, and should the period of theramp signal vary either greater or less than the desired base period,appropriate corrections are initiated by the feedback circuit from theoutput of ramp generator 21 to gate generator 20. Detailed circuitry forthis correction network is shown in FIG. 4.

The gate generator circuit 20 controls both the length and slope of theramp. A binary divider shown in FIG. 4 comprising flip-flops 41, 42, 43and 44 and logic gates 45 and 46 generates a gate signal 10 11 radianslong in this particular example. The binary divider sets the gateflip-flop 47 on some arbitrary first pulse from the 60 cycle line andsix pulses later resets the gate flip-flop. The long-short fiip-fiop 48is set at the beginning of the gate and reset when the ramp exceeds thenegative reference voltage by a small amount. The long-short flip-flop48 is compared with the gate flip-flop 47 to generate a positive voltageof fixed value for the length of time the ramp is longer than the gatesignal. Also, the same long-short Flipflop 48 is compared with gateflip-flop to generate a negative voltage of constant value for thelength of time the ramp is shorter than the gate signal. In the rampgenerator of FIG. 2, a long time-constant integrator shown in FIG. 5develops the correct output voltage such that the ramp slope iscontrolled to the correct value. The long-time constant integrator has apair of inputs representing the control signal as being either too longor too short. The ramp integrator has transistors in parallel with theintegration capacitor to set the ramp beginning and end point voltagesto equal the reference volt' age.

In the comparator of FIG. 2, the ramp signal is compared with the inputvoltage. When the ramp is equal to the input voltage and of oppositesign, the compare circuit output changes level. This triggers a one-shotmultivibrator shown in FIG. 6 which generates a sample pulse for twofield effect transistors. When the FET gate-to-source voltage is zero,the FET equivalent circuit is a simple resistance.

The modulation circuits 2S and 26 chop the sample-holdoutputs and thenintegrate the chopped signal to form the final output voltages.

Various modifications and variations of the present invention arepossible in light of the above teachings. It is therefore to beunderstood, that within the scope of the appended claims, the inventionmay be practiced otherwise than as specifically described.

1 claim:

1. A solid state multiplier comprising:

a gate generator responsive to any suitable source'of alternatingcurrent, said generator effective for producing a gating signalcorresponding to a predetermined number of cycles of the input ACsource;

a ramp generator electrically connected to said gate generator, wherebya linear voltage ramp is provided at the output terminal of said rampgenerator in response to and for the duration of each gating signal;

an analogue input signal source for providing a trigonometricrepresentation of the bearing and elevation angles of arrival of aninput signal ray;

a sample and hold circuit connected to the same input alternatingcurrent source as said gate generator;

comparator means for comparing said input analogue signal with said rampsignal and, upon detection of both signals being of equal value, forproviding a trigger signal to said sample and hold circuit;

said sample and hold circuit activated by said trigger pulse from saidcomparator means for providing an output signal indicative of the phaseand amplitude of said alternating current input signal at the instantthe ramp signal and the analogue signal are of equal amplitude.

2. The multiplier as set forth in claim 1, further including a feedbackcircuit from the output of the ramp generator to the gate generatorwhereby the period of the ramp signal is controlled both as to lengthand slope,

3The multiplier as set forth in claim 1, further including at least twosample and hold circuits, wherein both of said circuits are connected tobe simultaneously activated upon the receipt of a trigger pulse fromsaid comparator with each of said sample and holdcircuits beingconnected to said source of alternating current, one circuit connectedfor zero degree phase angle reception and the other circuit connectedfor phase angle reception thus providing sine and cosine functionsrespectively as output signals.

4. The multiplier as set forth in claim 2, further including at leasttwo sample and hold circuits, wherein both of said circuits areconnected to be simultaneously activated upon the receipt of a triggerpulse from said comparator with each of said sample and hold circultsbeing connected to said source of alternating current, one circuitconnected for zero degree phase angle reception and the other circuitconnected for 90 phase angle reception thus providing sine and cosinefunctions respectively as output signals.

5. The apparatus as set forth in claim 3, wherein the gating signalproduced by the gate generator is of rectangular form, said analogueinput signal takes the form of nrr cos a sin 0 where n 17 represents thewavelength or number of radians over which the interferometer basecovers and the angles a and 6 represent respectively, the angle ofincidence and angle of azimuth of an input ray to the interferometer.

6. The apparatus as set forth in claim 4, wherein the gating signalproduced by the gate generator is of rectangular form, said analogueinput signal takes the form of n 11' sin 6 cos a where n 1r representsthe wavelength or number of radians over which the interferometer basecovers and the angles a and 9 represent respectively, the angle ofincidence and angle of azimuth of an input ray to the interferometer.

1. A solid state multiplier comprising: a gate generator responsive toany suitable source of alternating current, said generator effective forproducing a gating signal corresponding to a predetermined number ofcycles of the input AC source; a ramp generator electrically connectedto said gate generator, whereby a linear voltage ramp is provided at theoutput terminal of said ramp generator in response to and for theduration of each gating signal; an analogue input signal source forproviding a trigonometric representation of the bearing and elevationangles of arrival of an input signal ray; a sample and hold circuitconnected to the same input alternating current source as said gategenerator; comparator means for comparing said input analogue signalwith said ramp signal and, upon detection of both signals being of equalvalue, for providing a trigger signal to said sample and hold circuit;said sample and hold circuit activated by said trigger pulse from saidcomparator means for providing an output signal indicative of the phaseand amplitude of said alternating current input signal at the instantthe ramp signal and the analogue signal are of equal amplitude.
 2. Themultiplier as set forth in claim 1, further including a feedback circuitfrom the output of the ramp generator to the gate generator whereby theperiod of the ramp signal is controlled both as to length and slope, 3.The multiplier as set forth in claim 1, further including at least twosample and hold circuits, wherein both of said circuits are connected tobe simultaneously activated upon the receipt of a trigger pulse fromsaid comparator with each of said sample and hold circuits beingconnected to said source of alternating current, one circuit connectedfor zero degree phase angle reception and the other circuit connectedfor 90* phase angle reception thus providing sine and cosine functionsrespectively as output signals.
 4. The multiplier as set forth in claim2, further including at least two sample and hold circuits, wherein bothof said circuits are connected to be simultaneously activated upon thereceipt of a tRigger pulse from said comparator with each of said sampleand hold circuits being connected to said source of alternating current,one circuit connected for zero degree phase angle reception and theother circuit connected for 90* phase angle reception thus providingsine and cosine functions respectively as output signals.
 5. Theapparatus as set forth in claim 3, wherein the gating signal produced bythe gate generator is of rectangular form, said analogue input signaltakes the form of n pi cos Alpha sin theta where n pi represents thewavelength or number of radians over which the interferometer basecovers and the angles Alpha and theta represent respectively, the angleof incidence and angle of azimuth of an input ray to the interferometer.6. The apparatus as set forth in claim 4, wherein the gating signalproduced by the gate generator is of rectangular form, said analogueinput signal takes the form of n pi sin theta cos Alpha where n pirepresents the wavelength or number of radians over which theinterferometer base covers and the angles Alpha and theta representrespectively, the angle of incidence and angle of azimuth of an inputray to the interferometer.